The development of an integrated circuit may include physical placement of functional blocks of an electronic design on the integrated circuit. For an application-specific integrated circuit (ASIC), various functional blocks may be placed within the area of the ASIC and the functional blocks may be interconnected by routing wires between the placed functional blocks. For a programmable logic device (PLD) integrated circuit, various functional blocks may be placed in programmable input/output and logic resources of the PLD and the functional blocks may be interconnected by programmable routing resources of the PLD.
The large number of possible placements of functional blocks of an electronic design may result in difficulty in finding a good placement that achieves the objectives for the electronic design. Consideration of even a small portion of the possible placements may not be practical. For example, consideration of a small portion of the possible placements using automatic generation of the placements may require more computational time than is practical. In addition, the best placement found in a practical amount of computational time during automatic generation may be significantly inferior to a good placement that is manually generated.
An automatic generation of a placement may result in a placement that does not match certain features of a manually generated placement. For example, a designer of a manually generated placement may systematically place related blocks. The apparently random placements from automatic generation may cause concern on examination by a designer. The placements of input/output blocks (IOBs) of the electronic design may be especially visible to designers because the placement of IOBs affects the design of a printed circuit board designed to carry the integrated circuit. An apparently random placement of IOBs may make development of the printed circuit board more difficult and time-consuming.
The present invention may address one or more of the above issues.